Stelar Tools Inc.
  HDL is Hard, We make it EASY!!
Analysis Engine
Ultra-fast parsing and analysis sytem.
 Approximately 60,000 lines of HDL/second
Full Verilog, Verilog 2001, and VHDL Support
Mixed languge support
Analyze incomplete (or syntatically incorrect designs)
Built in design metric analysis
Over 200 built in Best Known Methodology Checks
Design Connectivity Checks
Structural fanout analysis
Sunburst Design's Top Ten Rule checking
Fully customizable messaging system  
User created Best Known Methodology Checks  
Integration with third party EDA tools  
Graphical Environment
Design issues automatically back annotated into graphical environment
Advanced file list manipulation and back annotation
Hierarchical design tree browser
Library tree browser
Design data dictionary
Graphical Hierarchy design view
Design Connectivity View
Histogram analysis of your design
Fully enabled cross probing from graphical to text environments
Quickly find text in your across design environment
Integration with 3rd party editors
Automatically determine design location from built in text editor
Automatic Signal Routing and assignment  
Drag and Drop Module Instantiation  
Design Template creation and insertion  
Built-in support for popular editors (VI, Emacs, Brief, CoreWarrior)  
TCL Based API  
Script based control of the tool  
Command line (non graphical) version  
Automatically generate project files from your make system  
FlexLM Nodelock license support
FlexLM Floating license support  
  Copyright 2005 Stelar Tools.