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August 6, 2004


EDA startup readies a presimulation analysis tool

By
EE Times

May 21, 2004 (12:00 PM EDT)
 
SANTA CRUZ, Calif. — Larry Carner turned a misfortune into an opportunity. He was designing system-on-chip devices at Synopsys Inc. to prove the company's intellectual property worked as prescribed when he found some "holes" in the IC tool flow. Then the company downsized and he was on his own.

That gave Carner just the chance he needed.

Carner and Steve Sapiro founded Stelar Tools Inc. and put together a tool to fill the gap Carner had perceived in the IC design flow. Then they started to bounce the tool off customers to gauge their response. Stelar will announce plans this coming week to provide a presimulation design and analysis environment. The seven-person company, based in Portland, Ore., has received$1 million in seed funding and is now entering beta sites with its new tool.

After creating their tool, Carner and Sapiro came to the attention of Joseph Tanous, who was doing venture consulting at the time. "The more I looked, the more I liked, and I put in some seed money," said Tanous, a veteran of OrCAD Inc. and Mentor Graphics Corp. Several local venture capital firms decided to up the ante with more money, and Tanous became the startup's chief executive officer last November. Carner is chief technology officer.

Sapiro, who formerly worked at Intel, CAE Systems, Cadence Design Systems, Synopsys and Zycad, is vice president of marketing.

Tanous declined to provide details about Stelar's yet-to-be-announced tool, but he described its basic function. "It helps engineers doing HDL design to deal with complexity, and speed up the completion time of the design," he said. "It allows them to do some analysis and organization and understanding of the design up front, before they start pounding on the simulator."

Stelar's upcoming tool, Tanous said, will give designers a hierarchical, graphical view of a design, and allow some quick analysis and debugging. "It lets them use simulation for what it's intended for," he said.

The tool may defy easy categorization. Is it a design entry tool, debugging tool or lint tool? "Yes," Sapiro answered. "We're doing design creation, analysis, debug and documentation," Sapiro said. "Our goal is to reduce the number of simulation cycles before you run simulation." He said the tool can be used by both design and verification engineers, and that its use can start as soon as RTL coding begins.

For marketing, Tanous said, the company will use the same kind of indirect channel that was used by OrCAD, a provider of low-cost pc-board design tools. OrCAD's products are now sold through distributors in the United States. "We'll use the OrCAD model, do customer penetration through that channel and then use telesales," said Tanous, who promised that Stelar's tool will be "relatively low-cost."

Tanous said Stelar plans to roll out its product in late summer, and will have a suite at the 41st Design Automation Conference next month but will not publicly exhibit. He said the company currently has two beta customers, and hopes to expand to six or eight customers before releasing the product.

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